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IT8712F Revision Table

IT8712F Super I/O with Environmental Controller
Chip Feature Rev D Rev G Rev H Rev I

Chip Revision Register




Technical Specification Revision 0.4 0.6 0.7 0.81
Can support two IT8712F on the same board N Y Y Y
Reset issue with out of spec power supplies (note 1) Y N N N
Parallel Port Pins AFD#, STB#, INIT#, SLIN# are open drain N Y Y Y
Includes SMBus Y N N N
Fan Auto Mode Speed Set Three Steps Three Steps Linear Linear
Programmable Fan Startup Time N N Y Y
Fan Speed Change is Linear N N Y Y
Fan Tachometer Register 8 bit 8 bit 16 bit 16 bit
GPIO Pad and Registers on same Power Plane N N Y Y
Lockable Configuration Registers N N Y Y
Thermal Offset Register for Diodes (note 2) 1 global offset 1 global offset 1 offset for each diode 1 offset for each diode
Voltage ID Pins 5 Input Only 5 Input Only 6 In or Out 6 In or Out
Pin 53 (MTRB) is optional Thermal Output (note 3) N N Y Y
RSMRST# and PWROK1/2 (note 4) N N Y Y
PCI Reset Buffers (PCIRST1,2,3,4) (note 5) 0 0 1 - 4 1 - 5
PWROK 1 / 2 Delay N/A N/A 300~600ms 150~300ms  or 300~600ms
PCI Reset Input (PCIRSTIN) (note 6) N N N Y
KDAT, KCLK, MDAT, MCLK Pad Characteristics Open Drain 16mA Open Drain 16mA Open Drain 16mA Open Drain 24mA
Adjustable VID Threshold (note 7) N N N Y
VID Reference Voltage 3.3V 3.3V 3.3V 1.2V or 3.3V
ATX Power Good (ATXPG) (note 8) N N N Y
Full FanSpeed Hysterysis N N N Y
Fan Control 1 - 3 hardware controlled duty cycle (note 9) N N N Y
Number of Fan Controllers 3 3 3 5
Default PWM Frequency 48Khz 48Khz 48Khz 25Khz
Internal 5V VCC monitoring N N N Y
Temp outside range interrupt (note 10) N N N Y


1.  Some power supplies with wider than +/- 5% accuracy would cause reset issues
2.  Allows for compensation of differences in individual Diode Junctions
3.  Second floppy (B) is seldom used, so this is now an optional thermal output
4.  Resume Reset and Power OK 1 & 2
5.  Rev H has PCIRST 1 through 4 (4 is not enabled by default)
    Rev I has PCIRST 1 through 5 (all are enabled by default)
6.  PCIRSTIN# is muxed on pin91 and controlled by Index 2Ch[1].
    The outputs of PCIRST3# and PCIRST5# are (LRESET# AND PCIRSTIN#).
7.  Via power-on strapping.  Threshold value Vih/Vil = 0.8V/0.4V
8.  Modified PWROK signals with AND gated ATXPG x PSIN
9.  Power-on Strapping selects either 100% duty cycle for PWM
    -or- Startup at 100% and drop to 50% for noise reduction
10. If Temperature is Above "or" below range, interrupt is generated
    In previous versions, Interrupt was only generated if above range